Prepare for the lack of super-io UARTs and serialports on new mainboards

Kyösti Mälkki

Abstract

There are some common debugging problems people come across when starting a port of a new mainboard for coreboot. First is the flashchip being soldered on the mainboard and second is the lack of serial port connector. I attempt to attack both of these on some level. My primary goals are to add support for memory-mapped serial UARTs and the ECHI debug port mechanism on the commonly used payloads, and to integrate a pre-OS flash writing mechanism in the toolchain to allow easy and safe deployment of new coreboot builds.

Additional Information

Proposal timeline

This proposal includes ideas taken from 'coreboot panic room' and 'SerialICE' project ideas, and introduces a new idea for low-level tracing of PCI configuration using CBMEM. There would be a combination of new code development and porting of some of the new features from recent Chromebooks to older laptops and desktop boards. I would be looking at x86 architecture boards only.

Community bonding period

  • Evaluate and make decisions on which payloads would be relevant to have support added for memory-mapped serial UARTs and EHCI debug support. SeaBIOS, FILO, GRUB, memtest and u-boot should be considered.
  • Evaluate existing hack to use SerialICE with EHCI debug port.
    • SerialICE parser was simply copied to x201 mainboard romstage.c and hooked to usbdebug functions of coreboot. See http://review.coreboot.org/#/c/2663/8/src/mainboard/lenovo/x201/romstage.c

  • Evaluate the existing but not yet published patches for libflashrom, libpayload and FILO that implement some flash recovery mechanism.
  • Evaluate GSoC 2011 results for coreboot panic room.
  • Do effort estimation and adjust schedule accordingly.

Deliverables for mid-term evaluation

  • Add alternative bootblock for x86 that has capability to switch between boots to SerialICE console, flash recovery console, or a normal coreboot romstage. Selection is done based on a previous user event or board-specific GPIO signals.
  • Add support for memory-mapped serial UART and EHCI debug port consoles for selected payloads.
  • Build serialice.rom as a romstage for coreboot instead of a separate flash image under SerialICE tree. Reuse the coreboot tree structure and take advantage of all the superio and serial console setup code already implemented there.
  • Add memory-mapped serial UART support to selected SerialICE target boards.

Deliverables for final evaluation

  • Add early CBMEM and timestamping support for requested older mainboards.
  • Add EHCI debug port support for SerialICE target.
  • Capture selected PCI/IO/MEM transactions as coreboot executes through ramstage and log them in CBMEM table.
  • Add utility to read stored PCI/IO/MEM transactions from CBMEM and display them in format identical to SerialICE log output. Use logs to solve devicetree initialisation/traversal order issues that seem to hard to get right.

Development environment

Chromebook XE550C22-H02US (aka samsung/lumpy) with memory-mapped serial UART on mini-PCIe card to add console support for selected payloads. This hardware is also EHCI debug capable. I have previously used a do-it-yourself debug device with linux kernel but have not extensively tested it with coreboot.

To add early CBMEM and timestamping support for some older boards, I have an Aopen DXPL-Plus U board and a yet unpublished mainboard with Intel i915 MCH to experiment with. When it comes to porting existing early CBMEM implementation to other boards, I would primarily rely on the community to provide suggestions for the boards they are able to test on my behalf.

Code samples