License: New and Simplified BSD licenses
Mailing List: http://listmaster.pepperfish.net/cgi-bin/mailman/listinfo/lowrisc-dev-lists.lowrisc.org
lowRISC is a not-for-profit project to produce a completely open source SoC (System on Chip), with plans for volume silicon manufacture and low-cost development boards. We use the open RISC-V instruction set architecture, and are based at the University of Cambridge Computer Laboratory. lowRISC has its roots in the Raspberry Pi project, which two of the co-founders were heavily involved in.
The ultimate goals of lowRISC are:
- To create a fully open SoC and low-cost development board and to support the open-source hardware community. This will involve volume silicon manufacture.
- To explore and promote novel hardware security features
- To make it simple for existing companies and especially semiconductor startups to create derivative designs, e.g. by sharing scripts, tools, source and our experience
- To create a benchmark design to aid academic research
We are taking part in GSoC as an umbrella project, in collaboration with a number of other projects, either directly producing open source hardware or useful for developing open source hardware. You don't have to be a hardware designer to contribute, we have a range of projects in the hardware or software realm, in a variety of programming languages.
- Porting jor1k to RISC-V jor1k is an emulator for the OpenRISC platform and is the fastest emulator which runs in the web browser and boots Linux. At the highest level of abstraction main objective of the project would be to port jor1k to support RISC-V Architecture. Goals include booting Linux successfully, providing a web interface to test the compiled binaries, providing a demo file system with some major tools and adding support to some of the features of lowRISC such as minion cores.
- Porting seL4 to RISC-V Porting seL4 microkernel to RISC-V would assert this new powerful ISA hardware capabilities, exposing bugs and allow new hardware mechanisms (thanks to the open-source hardware flexibility) to be introduced. The project aims to port the small, but powerful, seL4 microkernel to RISC-V and this is of interest to both seL4 and RISC-V communities. Moreover, it will allow software L4 microkernel developers to interact with hardware designers narrowing the gap between each other.